High Performance Computing (HPC) is an important component for the European Innovation capacity and is also seen as an important element in the digitisation of European industry. The development of the next generation of HPC systems up to exascale computing means significant efforts in research and development in the field of HPC technologies, development environments and applications. Reconfigurable technologies such as Field Programmable Gate Array (FPGA) modules are becoming increasingly important because of their energy efficiency, performance and their flexibility. Future HPC systems not only have to cope with ever larger amounts of data because of their computing power, but also increasingly have to serve data-driven analysis applications (Data Analytics, Big Data) - often referred to as the merging of HPC and High Performance Data Analytics. In these areas in particular, HPC systems with heterogeneous architectures, including the use of FPGA accelerators, are therefore increasingly being used. What makes this technology particularly interesting is the ability to combine the enormous number of simple logic elements on an FPGA into complex, algorithm-specific processing units that work in parallel - the hardware "adapts" to the algorithm, unlike CPUs and GPUs. This removes the limitations of the von Neumann architecture of traditional computing platforms on FPGAs. The great flexibility also means that a large class of applications can be realised in HPC with FPGAs. FPGAs have also established themselves as the state of the art for high-volume data acquisition and processing in experiments (e.g. satellites, HEP experiments). Many years ago, the use of FPGAs in heterogeneous computer architectures was considered. However, the programming of FPGAs has so far mainly been reserved for specialists and is very time-consuming, which means that their use in the areas of scientific high-performance computing is currently still rare. Recent developments address the better coupling between FPGA-subsystem and host (Intel/Altera, Micron/Convey, ARM/Xilinx) and there are first steps to adapt the design cycle to the software development process (OpenCL for FPGA products from Altera and Xilinx). In order to use such architectures and those based on them effectively and efficiently, the software porting effort must be drastically reduced and common development concepts must be made available for use in HPC. In the HPC environment, there are a wide variety of approaches for programming models for heterogeneous computer systems with accelerators. Common programming models are, for example, OpenCL (opencl.org), OpenACC (openacc.org) and OpenMP (OpenMP.org) with cross-vendor initiatives, which so far are mainly aimed at supporting GPUs and many/multicore CPUs. OpenMP is the most widely adapted programming model to date. However, a productive usability of these standards for FPGAs is not yet given. Previous OpenMP implementation attempts have concentrated on the implementation of individual partial aspects and in particular do not address the performance aspects necessary for HPC. Further research is therefore necessary for the holistic approach, e.g. in the areas of new approaches in the representation of program codes and heuristic methods for optimization for inherently parallel architectures.

Goals of the project are:

• Development of an OpenMP 4.5 compiler targeting heterogeneous computing platforms with FPGA accelerators in order to simplify the usage of such systems.
• The completely new approach of designing and implementing a source-to-source framework that transforms C/C++ code with OpenMP 4.5 directives into an executable program that uses the host CPUs and FPGAs in a hardware-independent manner.
• Use and expansion of existing solutions of sub-problems for the optimal mapping of algorithms on heterogeneous systems and FPGA hardware.
• Research of new (sub-) solutions for heuristic methods to optimize program representations for inherently parallel architectures.